The present invention is in the area of DRAM memory systems. DRAM is a very widely used form of memory in computer systems today, and a useful reference for understanding DRAM and potential problems with its use is Microprocessor Based Design, by Michael Slater, Copyright 1989 by Prentice-Hall, Inc. Chapter 4, Section 4.7, pages 200-215 is incorporated herein by reference.
As may be seen in more detail in the pages of the reference incorporated above, each DRAM chip in a memory system is an integrated circuit with multiple transistor and capacitor elements that comprise an array of data cells. In operation of DRAM, to prevent data loss through charge leakage from the capacitor elements of the storage structures, data cells must be refreshed (energized) hundreds of times per second.
In a system with DRAM, a microprocessor-based CPU typically manages system operations, initiating read and write cycles to and from ZDRAM, and the CPU of such a system typically operates at a high frequency, the period for which may well be shorter than the cycle time for DRAM operation. The CPU must therefore impose time delays in its read and write operations to allow for delays in reading and writing DRAM. These time delays, called wait states, which are typically set according to programmed information in a system basic input output system (BIOS) at startup, may impose serious limitations on system performance.
The capacitive nature of DRAM has to be considered in a number of ways in system design and development. For example, charging and discharging of the capacitors in DRAM slows transitioning of address and control signals which interface directly with DRAM cells. Also, wiring DRAM chips in parallel increases capacitive load on address and control lines. In addition to these potential difficulties, row and column addresses are often multiplexed in high-performance computer systems to reduce the number of pins required for communication and control, and this circumstance increases the amount of time required to supply a complete memory address.
Many approaches have been taken by hardware and system designers to improve DRAM timing. For example, enhanced addressing and refresh techniques and signal path packaging are incorporated to minimize propagation delays. But these efforts have not completely solved the inherent problems.
In system design, wait states are typically assigned according to worst case expectations. This is a safe approach, since all other situations may be expected to fall within the worst case. In this approach, a system with a relatively light capacitive load may have the same delay restrictions imposed as one with a much larger capacitive load. For example, a 1-megabyte module with 4 chips might be needlessly slowed down by being assigned the same number of wait states as a 16-megabyte module with 36 chips. What is needed is a method to avoid the necessity for worst case assignment, so timing may be set more closely to actual circumstances.